1. Field of the Invention
The invention relates generally to digital multipliers and, more particularly to high speed combinatorial digital multipliers.
2. Brief Description of the Prior Art
High speed digital multipliers find application in digital signal processing in many applications, such as in real time processing of air traffic monitoring equipment, for example, wherein the controller needs to see planes on his screen immediately. Digital multipliers are also utilized in other digital signal processors, such as radar and sonar. In many applications, processing of analog signals in digital form in real time would not be practical without high speed digital multipliers. Other applications include fast Fourier transform processors and high speed floating point arithmetic logic units. The technology is such that a large number of power dissipating elements is required to implement a digital multiplier having an eight bit multiplier input and an eight bit multiplicand input, yet capable of operating at high speeds, such as 200 nanoseconds or less for a complete 8-by-8 multiplication. Prior art 8-by-8 multipliers required either several semiconductor chips, or if the entire multiplier were implemented on a single chip, excessively high power dissipation, thereby requiring forced air cooling. A strong need exists in the industry for an eight-by-eight digital multiplier which can be implemented on a single integrated circuit chip and housed in a conventional semiconductor package and yet dissipating only approximately one watt of power, and capable of operating at a speed of approximately 100 nanoseconds.